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Univers RTSIM is the stand-alone
RTL
Simulator. The RTL simulator is also part of Univers COVER. It is a blazingly fast
digital
simulator with a cycle-based kernel using 2-state logic
models or 4-state logic models,
resulting in simulations which are
factors faster when compared with traditional simulators.
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The Univers
RTSIM IDE
combines the following items to one
tool:
HDL
compiler & simulator: Verilog
or VHDL or both.
API to include
C++ models (peripherals, data
analysis,
...)
Many design views and
specific windows, see more below.
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Univers
RTSIM supports:
Verilog IEEE Std 1364-1995 and IEEE
Std 1364-2001
The full synthesizable VHDL syntax
The simulator supports
multiple asynchronous clocks. Tri-state signals are
supported by a 2-state model when fast execution is
required; a warning is given when a read
action is performed on a not initialized signals or
memory location. This indicates directly the source of a
(propagating) unknown.
It is fully supported to develop,
build and run test code or application code on a CPU
implemented in HDL code. For this purpose the
Application window and Disassembly window are included
in this RTSIM IDE.
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