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Today, systems contain one or more processors, a lot of memory
and a varying amount of additional logic, while the
amount of software running on these processors is increasing
dramatically. The embedded software is also increasingly
influencing the hardware, thus requiring that both
software
and hardware must be verified together. In stead of combining existing
tools to establish SW/HW co-verification, Adveda provides
ONE tool that will verify both the
software and the
hardware in one truly integrated environment.
Adveda calls this a UNIfied VERification
Solution and
has named it Univers.
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Univers COVER
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SW/HW co-verification (all-in-one tool)
Univers COVER is a complete
SW/HW co-verification tool for
multi-processor architectures, offering extensive
debug capabilities to guarantee
short development iteration cycles. The
application code runs on a full virtual system (high
speed) or uses partly the real HDL code for peripherals
or for your proprietary design.
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Univers ISSIM
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Multi-core Software Debugger
Univers ISSIM is a multi-processor development
environment, with fascinating debug capabilities.
C++ models are used for peripherals,
but also to model the environment (graphical LCD output,
stepper motor graphs, ...) or data analysis. Each
processor and peripheral runs on it's own user defined
clock signal.
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Univers RTSIM
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Stand-alone RTL simulator
Univers RTSIM is a blazingly fast
HDL simulator with a cycle-based kernel using 2-state
logic models, resulting in a 100x speed increase over
traditional simulators. Univers RTSIM supports
VHDL and Verilog. Special features are build in to
support multiple asynchronous
clocks, tri-state signals, etc.
while maintaining fast speed.
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Univers PROF2
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Accurate
Professional Profiler
The Univers Profiler
is a professional, accurate, static
and dynamic
profiling tool.
This profiler guides the decision making process
regarding high level and low level optimizations to meet
performance goals. Not based on inaccurate sampling
techniques. No code changes required for profiling
purposes. Shows all stall causes.
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HDL Navigator
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HDL Navigator
With the HDL Navigator
it is extremely easy to trace an HDL signal backwards and forwards. The HDL
Navigator is a dedicated HDL browser, which uses both
the source code and the compiled result.
Questions like: "What is the value of this parameter in this instance?" or "What are all the
destinations of this signal?" are directly answered.
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Simulation Models
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Instruction Set Simulators
A growing number of Instruction Set
Simulators is available for Univers:
ARM, PowerPC, MicroBlaze (Xilinx), NIOS II (Altera), AVR,
8051, etc.
Adveda has developed these ISSs and we
can develop an ISS for your specific CPU, ranging from
sequencers to complex vector processors. Ask for a
quotation!
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SL2 Compiler
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System Level
Specification Language (SL2) Compiler
SL2 is an abstract descriptive
language, developed to create fast cycle true
simulation models of processor cores.
The ISS automatically
connects to the Univers tools.
Using the SL2 compiler is extremely efficient for
architectural design exploration before the hardware
design is
started.
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