SL2 compiler available for modeling CPU's, DSP's and Sequencers

General Description

SL2 (System Level Specification Language) is an abstract descriptive language, developed to generate fast cycle true simulation models of processor cores and peripherals, suitable for multi-core firmware development environments. As the potential of the language is more versatile, it is extending to a complete SoC modelling and specification language.
 
The SL2 language is used within Adveda to create the Instruction Set Simulators. The approach of using SL2 has proven to be 8 to 10 times faster in development time, thus leading to:
high costs reduction with guaranteed high-quality results,
generation of more ISS's in shorter time.
 
The methodology of describing processors in SL2 has several major advantages:
Highly reduces the development time of the processor model (ISS)
Enables design exploration and trade offs; without implementing the processor
   The SL2 compiled model connects automatically to the Univers debugger
   Within Univers all features are available to explore the processor
The SL2 model can be used as the golden reference to automatically verify the RTL implementation. For this purpose an automated test generator is available.


Features

Complete modeling language to model any kind of hardware
Economy of expression
Modern control flow leading to fast executing simulations
Rich set of SW and HW oriented data structures
Rich set of operators and user definable operators to model side effects
Economy of generated code with respect simulation speed
Built in support for any type of processing unit (RISC, DSP, VLIW, SIMD, ...)
Built in support for run-time ISS reconfiguration
Built in support for extremely fast data transfer between created models
Built in support for high abstraction level bus interfaces
Built in support for signal creation and seamless integration with RTL simulator
Integrates automatically and seamlessly with Adveda's simulation and debug tools

Multi processor SoC

The SL2 Compiler generates machine-independent C++ code, which can be compiled to any platform with a C-compiler of choice. On top of it, it wraps this model with its database into a debug API, which hooks directly into Adveda’s Integrated Development and Debug Environment (Univers IDE).

Univers ISSIM:  Multi-core simulation IDE includes SL2 generated ISSs and peripherals. Univers COVER: Combines Univers ISSIM with an HDL simulator (VHDL and Verilog).


Runtime configuration

Runtime configurations allows the user to switch architecture by just a couple of mouse clicks, rerun the simulation and evaluate the profiling output to choose the best architecture suitable to do the job.

When the Altera NIOS II CPU is taken as an example, it means that the software engineer can easily change CPU type (economic, standard, fast) within the Univers tools, change cache availability and size, etc to be able to chose the best architecture. This results in being able to select the most cost efficient FPGA for the application.


Technology

The SL2 language itself is a high-level description of the collection of hardware resources (registers, memories and operators) without a description on how they are connected. The connections between these resources are implicitly described by the instructions.  The instructions also contain the disassembly text that are made visible in the disassembly window of the debug environment. 

The SL2 language together with the SL2 Compiler is a very efficient technology to build and maintain a variety of simulation models of processor cores and peripherals.

There are more languages to describe the behavior of a processor. When these languages describe a cycle-accurate model, it is often required to divide every instruction in parts and describe each part of the instruction in each stage of the pipeline, separately. This requires a lot of detailed modeling on a lower level, which consumes more valuable time than using SL2. SL2 is not an extension to C++, it is a modeling language.

SL2 is unique, because the instruction is executed as a whole and the behavior within the pipeline is defined by the storage elements. SL2 supports an easy method to define at what time the actual storage elements will get the updated value.

Besides that, it makes the ISS much faster, it also provides an easier programming model for the SW engineer, as a halted instruction is always fully executed and the fact that the execution will be valid in the future, is made visible within the simulator.

 

More info

 

If you require more information you can ask Adveda, click here.

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