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Univers COVER is the development tool for creating and
verifying systems which include one or more CPU's and HDL designs.
The Univers COVER IDE combines the following items to one tool:
 One or more CPU's models (Instruction Set Simulators)
API to include C++ models (peripherals, data analysis, ...)
HDL compiler & simulator: Verilog or VHDL or both.
Many design views and specific windows, see more below.
Univers COVER is the ideal solution to have the System Engineer,
Software Engineer and Hardware Engineers work together with one and the same tool. The
hardware engineer can use the Hardware Abstraction Layer
(HAL) software immediately to verify the hardware from the CPU level instead of
using a limited bus functional model. The HAL software is tested at the same time. Software views can be
created by each engineer to ease debugging. For high speed system level development purposes a C++ model is
attached to the ISS. This model can be created before or after the creation of the HDL design, dependent on the
project requirements. These models provide full visibility and controllability and they can include additional
features such as graphical LCD output.
The tools are build for user convenience, providing full
controllability and visibility of a complete system. User convenience includes also providing a short iteration
cycles to developers. The iteration cycle is within SW/HW co-verification dominated by the speed of the
digital simulator. Adveda has succeeded to build an ultra fast digital simulator, extremely suitable to be
used for SW/HW co-verification. This simulator supports many unique features, while maintaining the speed.
Compared to mainstream digital simulators the Adveda simulator is between 5x to 100x faster, dependent on the
coding style and type of design.
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