Adveda - Chip design verification: Hardware, Software, RTL Simulator, VHDL

Introduction

Tools from Adveda provide a virtual workbench to develop and/or debug the combination of software and hardware.

Multiple different Instruction Set Simulators (ISSs) of CPU's in combination with HDL code simulate factors faster compared to mainstream digital simulators.

SW and HW engineers can both use the convenience of the same productive and user-friendly IDE. Reduces failure rates. Increases communication between disciplines.

The Univers tools provide an unmatched rich and unique set of awesome features to ease design exploration and (system) debugging.

The reduction of the development time and the increase of the First-Time-Right chance guarantee a splendid Return-On-Investment.

Unique selling points:
Real multi processor development/debugging
Highly effective: full visibility/controllability
Cycle accurate models
Virtual workbench, no hardware required
One tool for SW and HW development
All time full insight in the design state
Fully extendible to model the environment
Automatic embedded OS support
Etc, see product pages or call us

News

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Univers v2.20 is now released:
+ Includes Verilog
+ Configurable peripheral models
+ Static/Dynamic Profiler
+ HDL Navigator
+ Step and Compare verification

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Different ISS's, such as:
ARM, PowerPC, MicroBlaze (Xilinx), NIOS II (Altera), AVR, 8051, and more.

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High speed ISS for Altera NIOS II
Full support for e,s and f type, including caches, customer instructions (HDL), avalon bus models, disassembly, etc...

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Tutorial movies demonstrating some of the features of the Univers tools.

Products

Simulation/Debug tools:

Univers COVER

Univers ISSIM

Univers RTSIM

Univers Add-on:

Univers Static/Dynamic Profiler

HDL Navigator

CPU model (ISS) creation:

SL2 Compiler